This invention relates to ultrafast electronic circuits for digital signal processing. There is a constant need for circuits which can operate at extremely high speed. A technology which offers ultrafast operation is the rapid-single-flux-quantum (RSFQ) logic technology which is based on the use of superconducting Josephson junctions (JJ's). This technology operated at cryogenic temperatures provides the fastest digital circuits in any electronic (non-optical) technology. For example, simple circuits formed in this technology can operate at over 700 GHz and complex clocked circuits have been demonstrated to operate in the range of 40 GHz. These circuits are based on the distribution of narrow picosecond pulses between logic gates. A problem with these circuits is that due to these high speeds, precision timing in the clock distribution is critical.
This invention also relates to the design of circuitry which may be used, for example, to form a digital interpolation filter (DIF) or a digital decimation filter (DDF). The block diagram of a DIF of interest is shown in FIG. 1. The DIF shows an m bit word applied to the m-bit cells of the k differentiator circuits 100 to provide k stages (1 through k) of differentiation of the input signal at a slow clock (SC) rate (e.g., f/2n). The outputs of the kth stage are applied to a “resample unit” (RU) 200 that increases the sample rate, followed by k stages of integration circuits 300 (1 through k) at a fast clock (FC) rate (e.g., f). (The numbers of integration and differentiation stages are matched to avoid signal distortion.) The simplest zeroth-order (k=0) DIF would consist of just the resample unit, but the output would be a crude step-like function. A first-order (k=1) would have an output that interpolates linearly between the input points, while k=2 interpolates quadratically. Additional stages provide additional levels of interpolation.
Suitable differentiator and resample circuits have not previously been implemented in the RSFQ technology. Critical aspects in the design of suitable circuits is that they provide a desired function and precision timing in the distribution of the clocking signals and that they be reasonably simple to manufacture and be made up of cells which can be readily interconnected to handle multi-bit signals (words) of different size.